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Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Nothing unexpected
Computer Architecture, Logic design, validation, software, behavioral.
Black-box vs white box testing, techniques used while verifying designs, system verilog constructs related to verification, UVM OVM etc
Difficult technical questions, very unforgiving when I got one question wrong, they ended the interview straight away after that.
The first interview related to the introduction about both parties and a personality check of the candidate
about UVM, explain project (it was on UVM) , basic object oriented concepts like abstraction, constructor, function overloading
functional coverage, types of bins, types of array, constraint examples, virtual class,threads
Most of the interview questions were from my resume and projects i have done. Some of the questions were based on VLSI design concepts
About me, school projects and all content in CV. Communication protocols and signal analysis Algoriths known
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