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Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
My previous experience, basic assertions and fifo programming
Describe coverage types, describe comlexity of environmentst that you work so far, UVM reg model
uvm basic, ovm basic and python
Not really difficult, jut really technical
Round 1: 1. What is Functional Verification? Round 2: 1. What is the difference between Verilog and System Verilog? 2. What is the difference between Blocking and Non-Blocking assignment? 3. What is an FSM 4. Mealy and Moore machine 5. What is the difference between synchronous and asynchronous design? 6. Verification using test environment 7. UVM testbench 8. Synthesis design model 9. Critical path 10. Setup time and Hold time 11. Metastable state And some more verification related stuff
Formal verification basics, writing assertions, etc.
Uvm related Project related Sv concepts Fifo full empty conditions Fork join concepts Axi ahb difference
find the minimal number of semi-binary numbers that sum up to a given number. semi-binary is an integer that is composed only by the digits 1 and 0.
HR interview were standard questions. Interview with manager were more technical and based on testing and previous experiences
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