Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
about projects, verification methodologies, UVM, System Verilog testbench, Computer Arch, MESI protocol, Cache UVM testbench components, constructs Digital Design questions FSM types and differences Divided by 2 clock design and code Basic Gate level designs
Programming, queries, test cases, aptitude
Questions about debug of failure
polymorphism in system verilog and virtaul interfaces.
about how to build an adder
One medium question on leetcode. Absolute software engineer question.
FiFo depth, Assertions, FSM, Clocks
Write a Scoreboard for verifying the average of 5 previous values, where the data is coming sequentially, I.e 1 value at every posedge of clk.
UVM questions. SVA questions. UPF questions. Short path algorithm between A and B Sorting array algorithm Give you basic design and ask you for verification plan, how will you implement scoreboard , why that choice... Question about blocking/non blocking assignment
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