How to design a two stage band-gap amplifier
Digital Design Engineer Interview Questions
553 digital design engineer interview questions shared by candidates
Generate a pattern 1101
Filter design questions (pole/zero placement). Static Timing Analysis question between 2 clock domains. Convert this circuit into only NOR gates.
Static timing analysis and finite state machines were the major focus
factorial of a number
Asynchronous fifos, critical path timing, formal verification, clock gating
What are glitches. How would you get rid of them in a digital signal?
Given a white-board diagram of a block with a FIFO, and verbal description of the block's inputs & outputs, write on the withe board the Verilog or SystemVerilog for the design. I had 15 minutes. Why would you want someone who goes straight to code, with no planning? That usually results in spaghetti code that has to be rewritten.
K-map simplification, sense amplifier, charge pump, operative phase of DRAM, semiconductor reliability(NBTI, HCI)
What is an CMOS inverter and its waveforms
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