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Digital Design Engineer Interview Questions

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553 digital design engineer interview questions shared by candidates

During the phone interview, I was asked about some concept questions on out-of-order execution and cache. Asked me to describe reorder buffer, history file, and future file. Also talked about Tomasulo Algorithm. Had to do an IQ test online before the on-site interview... There are about 6 rounds during on-site. Meet with the management team, including a few higher level managers. Mostly discussed my previous experiences and projects. Only two rounds are technical, in which one round, I discussed out-of-order execution again (still those topics, reorder buffer, history file, future file, Tomasulo, etc. ). In the other one, discussed the memory access of out-order-execution. Basically, during an out of order execution, what if after a memory write go through, a dependency is discovered (in other words, we write to the wrong memory address). Interview is really on the easy side, comparing to Nvidia's and Apple's.
avatar

Digital Design Engineer

Interviewed at IBM

3.9★
Nov 30, 2017

During the phone interview, I was asked about some concept questions on out-of-order execution and cache. Asked me to describe reorder buffer, history file, and future file. Also talked about Tomasulo Algorithm. Had to do an IQ test online before the on-site interview... There are about 6 rounds during on-site. Meet with the management team, including a few higher level managers. Mostly discussed my previous experiences and projects. Only two rounds are technical, in which one round, I discussed out-of-order execution again (still those topics, reorder buffer, history file, future file, Tomasulo, etc. ). In the other one, discussed the memory access of out-order-execution. Basically, during an out of order execution, what if after a memory write go through, a dependency is discovered (in other words, we write to the wrong memory address). Interview is really on the easy side, comparing to Nvidia's and Apple's.

I found most of the questions pretty simple. I am categorizing all the questions below for reference. 1. Latches - Flip Flops 1. Basic operation 2. Setup and hold time - especially for latch 3. Meta stability 4. Code in verilog 5. How to avoid unintentional latches 7. Problems with SR latch and how are they solved 2. FIFO 1. Constraints on reading and writing pointer 2. Size of fifo for given input and output frequencies 3. FIFO for data and address buses 4. How to synchronize? 3. Design 1. Asynchronous and synchronous reset in Flip Flops 2. Data(D1) following data(D) while going low (asynchronous) but synchronous with clock while going high 3. ADC Design 4. Sensitivity list - if missed what is implication on gate level simulation 5. Clock by three 4. DFT 1. Explain DFT 2. Scan Chains and Scan FFs 3. Fault models 4. Delay fault 5. Testing of two clock counters by adding logic in between to reduce overall time. (First counts from 0 to 255. For every 256 counts in first seconds increments its counter by 1.) 5. Verification 1. Test plan 2. Assertions 3. Coverage - when will you stop verification 4. Layered test bench 5. Randomization 6. Difference between rand and randc. 7. where is randc used? - decoder verification 8. Classes and objects 7. Computer Architecture 1. Explain stages of pipeline 2. Cache design 3. Associativity of cache 8. ASIC 1. Explain ASIC flow 2. Explain DRC and LVS 3. Explain synthesis script 1. Constraints 2. Goals 3. clock 4. setup and hold time
avatar

Digital Design Engineer

Interviewed at Analog Devices

4★
Dec 6, 2014

I found most of the questions pretty simple. I am categorizing all the questions below for reference. 1. Latches - Flip Flops 1. Basic operation 2. Setup and hold time - especially for latch 3. Meta stability 4. Code in verilog 5. How to avoid unintentional latches 7. Problems with SR latch and how are they solved 2. FIFO 1. Constraints on reading and writing pointer 2. Size of fifo for given input and output frequencies 3. FIFO for data and address buses 4. How to synchronize? 3. Design 1. Asynchronous and synchronous reset in Flip Flops 2. Data(D1) following data(D) while going low (asynchronous) but synchronous with clock while going high 3. ADC Design 4. Sensitivity list - if missed what is implication on gate level simulation 5. Clock by three 4. DFT 1. Explain DFT 2. Scan Chains and Scan FFs 3. Fault models 4. Delay fault 5. Testing of two clock counters by adding logic in between to reduce overall time. (First counts from 0 to 255. For every 256 counts in first seconds increments its counter by 1.) 5. Verification 1. Test plan 2. Assertions 3. Coverage - when will you stop verification 4. Layered test bench 5. Randomization 6. Difference between rand and randc. 7. where is randc used? - decoder verification 8. Classes and objects 7. Computer Architecture 1. Explain stages of pipeline 2. Cache design 3. Associativity of cache 8. ASIC 1. Explain ASIC flow 2. Explain DRC and LVS 3. Explain synthesis script 1. Constraints 2. Goals 3. clock 4. setup and hold time

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