Digital Design Engineer Interview Questions

553 digital design engineer interview questions shared by candidates

How to synchronize a data bus, which has no control. Interviewer was basically trying to poke at the approach to solve that problem. Write clock domain has a burst rate of 80 writes per 100 clocks. Read clock domain reads at a rate of 8 data words in 10 clocks. Data Buffer sizing to not cause overflow Asked to design a 2 request arbiter.
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ASIC Digital Design Engineer

Interviewed at Synopsys

3.8
Jun 16, 2018

How to synchronize a data bus, which has no control. Interviewer was basically trying to poke at the approach to solve that problem. Write clock domain has a burst rate of 80 writes per 100 clocks. Read clock domain reads at a rate of 8 data words in 10 clocks. Data Buffer sizing to not cause overflow Asked to design a 2 request arbiter.

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