Digital Design Engineer Interview Questions

553 digital design engineer interview questions shared by candidates

Aptitude (20 questions) – Time, speed, ratios, basic probability Embedded MCQs (20 questions) Bitwise operators Memory mapping C pointers and arrays UART/SPI/I2C basics 1 Coding Problem Write an interrupt-driven LED blinking program in C using pseudo-registers
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Digital Design Engineer

Interviewed at Texas Instruments

3.8
Jul 29, 2025

Aptitude (20 questions) – Time, speed, ratios, basic probability Embedded MCQs (20 questions) Bitwise operators Memory mapping C pointers and arrays UART/SPI/I2C basics 1 Coding Problem Write an interrupt-driven LED blinking program in C using pseudo-registers

Texas Instruments (Digital ) Interview Experience : 1. Introduce yourself 2. Asked to explain a course project . Asked details of it including the finer implementations . They went quite deep into the project. 3. Asked to explain another project. 4. Draw a circuit to count the number of 1’s in a vector. Asked to optimise it after I gave a not so optimum solution. 5. Draw a circuit to implement a given pattern (don’t remember it now) . Input and output was given . You have to detect the pattern from input and output and draw the digital circuit accordingly. The pattern was such that for the even no. of clock pulses , out=in but for odd clock pulses , out =in_delayed_by_2 (in value 2 cycles ago)
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Digital Design Engineer

Interviewed at Texas Instruments

3.8
Dec 4, 2022

Texas Instruments (Digital ) Interview Experience : 1. Introduce yourself 2. Asked to explain a course project . Asked details of it including the finer implementations . They went quite deep into the project. 3. Asked to explain another project. 4. Draw a circuit to count the number of 1’s in a vector. Asked to optimise it after I gave a not so optimum solution. 5. Draw a circuit to implement a given pattern (don’t remember it now) . Input and output was given . You have to detect the pattern from input and output and draw the digital circuit accordingly. The pattern was such that for the even no. of clock pulses , out=in but for odd clock pulses , out =in_delayed_by_2 (in value 2 cycles ago)

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