explain last project
Asic Engineer Interview Questions
1,075 asic engineer interview questions shared by candidates
design a divide by 3 divider
The first one was about implementing a NOT gate with MUX.
for phone interviews, basic data structure algorithms. 1. Reverse singly linked list. Onsite was more difficult with a bit of algorithms, computer architecture, design verification, and OOP.
How do you as a back-end designer work with front-end (RTL/Synthesis) designers to solve tough timing problems, for example, under what circumstances do you absolutely need them to solve on their side? What information or files do you provide to them?
Phone interviews : CMOS basics, usual some gate/logic using one gate, timing related questions, FIFO depth, max in array, palindrome Onsite : CDC - a lot on various techniques and improvements from one to another, clock MUX logic, Clock dividers, FSM , Timing related question based on designs above
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
Asked about Cache implementation (since I had a project on cache implementation using verilog)
In C, write code to find out if a string is palindrome or not
Asked basic questions based on resume. The position required CPU architecture knowledge. I hadn't taken any of those courses, so interviewer asked only IC designing questoins.
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