Code for fsm,digital electronics and sta
Verification Engineer Interview Questions
2,558 verification engineer interview questions shared by candidates
Draw an AND gate using transistors.
What are the limitations of current design methodologies?
Design a digital circuit that on every third cycle calculates the average between the first and the second posedge and write it in verilog
UVM and verification questions mainly
1) Tell me about yourself 2) Tell me about the projects on your resume
-General digital flow design -General UVM verification questions
1.difference between dynamic,static ,short circuit power diddipation ,where and how it happens ,how to reduce them 2. power reduction technoques at logic and architectute level 3. verilog
UVM Concepts and Work Experience of previous project
How we can integrate agents without them generating stimulus
Viewing 2431 - 2440 interview questions