System Verilog and Formal Verification
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
Draw a FSM sequence detector
What is your greatest weakness?
digital circuits and verilog , c language
Given an error message, what could be the issue.
Microprocessors, flipflops.
A design has 2 types of cmds - read and write packets. You need to send 10 back to back cmds through a sequence in such a way that after a write cmd was previously sent, you cannot immediately send a read cmd. However, the 1st cmd sent can be write cmd.
Conflict in team? Time management?
What is deep copy and shallow copy in System Verilog? Can you tell about sequencer in UVM and what is the use of it? What is virtual interface and why it is used? Gave a Constraint and asked what will be the randomised values. Asked to write an assertion for a given scenario Asked to write a constraint such that it will generate even and odd numbers in sequence.
Code for fsm,digital electronics and sta
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