"know that what you are going to do here, you won't be able to reuse in other companies"
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
UVM environment and how it works?
they asked basic vhdl questions
Q: How to be creative?
Do you know how to parse directories in Python?
They asked the questions about uvm & system verilog.
Verify the Round Robin arbiter with priorities. Find nth maximum number in an array They gave various designs and asked me how would you verify it. Write the code for the scoreboard. What kind of challenges you will face while verifying the design? What is polymorphism in SV? Where do you use it? 2 x 2 router verification. In-order and out-of-order. They asked me to write the constraints for some cases for eg write followed by read on the same address. It looks like a important part of their interview process.
State Machine. How to verify a piece of logic.
Design memory in C++
There weren't any very difficult or unexpected questions.
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