Given waveform of input signals and combinational and sequential circuit and question was to draw wave of output signal.
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Uvm, system verilog
How do you handle the arbitration for multi master and multi slave in apb protocol
In general, what kind of persons you don't like to work with?
Basics of digital verilog projects and academics project
Write a verilog code for dual Port ram using 2 single port ram
Can you insert a function inside a function? If yes, how?
Logical questions, counter implementations constraints
sv uvm questions , sequencer grab , uvm topology etc
uvm and sv questions , sequencer grab etc
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