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Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Basic questions about verilog and system verilog
1. Power dissipation in BJT 2. Timing diagrams 3. MOSFET operation
Can you just Introduce yourself
polymorphism, SV basics, coverage, assertions, UVM testbench flow
What is the reason you go for a PVT on SoC and what is the criteria you need to consider for validating the SoC
Introduce your school projects
basic setup hold time
What is synchronous and asynchronous reset? Setup time and hold time
Intraduse About project Verilog code
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