what is blocking and non blocking?
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
There were 4 rounds - 3 technical and 1 HR.
Constraint and assertion , gate level simulation
mostly in uvm and sv
Verilog based questions - circuit was given and then i had to give an optimized code for it.
Power of 2, asynchronized and synchronized reset
Verify a packet processing DUT where packets coming in have a certain priority.
Explain about FIFO, Clk generation, State machine
Given an array of N elements and an array of M elements, both sorted in ascending order, create an array C that combines A and B in ascending order.
On projects and sv uvm based Protocol knowledge on what we mentioned in resume
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