Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
They gave a class - asked to create it's objects and send out random objects in a function.
What will affect power consumption?
Explain the latest project you undertook.
Sv constraints on memory block and region. GLS questions on debug flow.
Develop a C algorithm to solve arbitration in bus
How instructions are executed in assembly language? How data is transferred between cpu and cache? Why we need cache, why we don't use main memory? Why cache size is kept small?
For the design verification interview, I haven't prepared at all since I didn't know that it was a verification position, all the questions about programing were not answered well.
Basics of computer architecture, verification, data structures, rtl logic Telephonic interview was basics of RTL design
question on packet transfer inside of test bench from generator to driver... (system verilog concepts)
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