f/3 counter design using FSM
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
they focused a lot on OOP, which is unexpected given the title that I applied.
Do you know anything about RISC Architecture?
1. Write a constraint to generate 4 variables which are unique
How would you write a test with randomized input (with bounds)?
Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
C++ related Questions
Design scoreboard to compare dut and reference model.
Write SV assertion for a req/ack protocol
UVM , system verilog and scoreboars related questions.
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