Topics like pipelining & hazards, Cache, Assembly language, VHDL, C, frequncy divider, clock gneration using VHDL are touched in the technical rounds. And a question to explain my project from digital design is asked.
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
digital electronics and verilog
How would you debug a failing simulation where coverage is not met?
Basic question in SV, UVM, Verilog, Linux
Implement Coverage for given scenario
how to balance the pipeline stage to achieve any specific time period?
A question about managing branching methodology when dealing with IP cores.
Compare Superscalar and VLIW processors.
Why did you not raise alarm on a certain issue? (I didn't think it was that important, but the interviewer thinks it is very important - again a smile that hints that my team is not doing the right thing, according to him).
FSM: Pattern detection 101 in a given sequence --> Change design from Moore to Mealey machine; Lots of questions based on Computer Architecture ( Memory-Cache heirarchy), Test Case scenarios, Signal Tx-Rx rates based question,
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