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Soc Design Engineer Interview Questions
100 soc design engineer interview questions shared by candidates
1. Static and dynamic power 2. How to fix setup and hold time violation without adjusting clk frequency? 3. Significance of VT 4. Subjects of 1st and 2nd semester in mtech. 5. RTL to GDSII 6. Basics of design for testability.
Explain stuffs in my resume
Pipeline stages in common computer architecture. Why does it has to be 5 stages? Critical path solving question with 5 cascading xor gates.
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
How transistor works and design logic circuit base on a problem given ?
Write a scoreboard in SV or UVM for simple alu where there is an 8 bit input that is changing value every clock cycle and the output should be equal to sum of previous 5 inputs.
Write a test plan for asynchronous reset flip flop
Design a clock divided by 3. Design a synchronous FIFO, Sequence Detector
Questions on how to micro-architect linked list memory
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