what is a uvm agent?
Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
Resume questions, fifo questions, assertions, coverage
First interview: describe a FSM for the result of a sequence of binary input mod 5. Merge sort. Second : C/ verilog coding.
Write a test plan for asynchronous reset flip flop
Online interview: 1. What is polymorphism ? 2. Design a 3 bit shift register in verilog RTL ? 3. For a FIFO design, what kind of assertions will you write(what conditions would you check for proper functioning of the FIFO) ?
introduce yourself and why you want to work at apple
Design, Test plan, SystemVerilog ......
SV, UVM, Driver sequencer handshake mechanism
There was no tehnical interview for no experience engineer
How many quarters would it take to stack end to end from the ground to the top of the empire state building. State your assumptions.
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