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Design Verification Engineer Interview Questions
951 design verification engineer interview questions shared by candidates
design question - design a system to identify if input bitstream is divisible by 5 - taking a 16bit stream, programming - print matrix spiral, etc. Also assertion questions, UVM
Describe fully how a processor works in as much detail as possible.
Edge trigger variation coding in RTL
Write a test plan for asynchronous reset flip flop
introduce yourself and why you want to work at apple
Design, Test plan, SystemVerilog ......
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
Implement a circuit board the receives an 8-bit bus. The output is an 8-bit bus where the first net that is '1' in the input is also '1' in the output, the rest are '0' (in other words - "find first '1' in the input bus).
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