Verilog: Difference btw sequantial and combinational logic. Difference btw blocking and non-blocking assignment.
Circuit Design Engineer Interview Questions
118 circuit design engineer interview questions shared by candidates
RC circuits.
About RC circuits and explain their behaviour intuitively
What are "Spare Cells" and why it is used? Why do you make clock as Ideal during floorplan & Placement Stage? What are the different Checks we do in the CTS stage? What if Setup is failed after manufacturing of chip? How will you fix Hold? What is the Importance of useful Skew? What are DRV Checks and why do we check that? What is the cross talk? How it will effect the performance? Cross delay or Cross talk noise is note generally. Why? A Blocks having 7 Metal layers and same block having 10 metal layer, which will function better and why? How will you define the shape of the Die?
Types of Noise that affect an Op-Amp. How may we can reduce the affect?
Resume questions. Mostly about computer architecture project.
How to convert a Nand gate to OR gate.
At first device, NAND, NOR gates, I am fine. But later mostly digital, I forget those latches, flip-flop. It is easy, but I am not well prepared. This is my first phone interview.
Plot waveform of inverter characteristic
Implement a system that get 2 clock inputs faster and slow, and outputs a '1' when the fast clock is 50 times faster than the slow clock.
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