Circuit Design Engineer Interview Questions

118 circuit design engineer interview questions shared by candidates

Other than what people have posted, they asked me Step and ramp responses for a RC-Low pass and RC-high pass filter. What frequency components does slow varying ramp has? Building basic gates from 2*1 Mux. Inverter with feedback and input resistance, how does the Vm of the inverter vary?
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Circuit Design Engineer

Interviewed at Analog Bits

4.2
Feb 9, 2016

Other than what people have posted, they asked me Step and ramp responses for a RC-Low pass and RC-high pass filter. What frequency components does slow varying ramp has? Building basic gates from 2*1 Mux. Inverter with feedback and input resistance, how does the Vm of the inverter vary?

Would an inverting or non-inverting amp be better for noise reduction? How might one amplify a photodiode sensor? How does a pyroelectric sensor work? How does I2C/SPI work? What's the BW and gain for ...? Draw a block diagram of the AFE for a sensor with ...?
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Circuit Design Engineer

Interviewed at Coherent Corp.

3.4
Oct 29, 2020

Would an inverting or non-inverting amp be better for noise reduction? How might one amplify a photodiode sensor? How does a pyroelectric sensor work? How does I2C/SPI work? What's the BW and gain for ...? Draw a block diagram of the AFE for a sensor with ...?

What are "Spare Cells" and why it is used? Why do you make clock as Ideal during floorplan & Placement Stage? What are the different Checks we do in the CTS stage? What if Setup is failed after manufacturing of chip? How will you fix Hold? What is the Importance of useful Skew? What are DRV Checks and why do we check that? What is the cross talk? How it will effect the performance? Cross delay or Cross talk noise is note generally. Why? A Blocks having 7 Metal layers and same block having 10 metal layer, which will function better and why? How will you define the shape of the Die?
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SRAM Circuit Design Engineer

Interviewed at TSMC

3.3
Apr 5, 2024

What are "Spare Cells" and why it is used? Why do you make clock as Ideal during floorplan & Placement Stage? What are the different Checks we do in the CTS stage? What if Setup is failed after manufacturing of chip? How will you fix Hold? What is the Importance of useful Skew? What are DRV Checks and why do we check that? What is the cross talk? How it will effect the performance? Cross delay or Cross talk noise is note generally. Why? A Blocks having 7 Metal layers and same block having 10 metal layer, which will function better and why? How will you define the shape of the Die?

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