Frequency divider
Asic Engineer Interview Questions
1,076 asic engineer interview questions shared by candidates
Setup hold time calculation
CMOS characteristics?
To print out elements on 1/8th of the circumference of the circle
Design a async fifo for a given freq and throughput.
what do u know about virtual pages
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Constraint randomization based question linking to AXI and memory filling
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