What are RTL, Gate, Metal and FIB fixes?
Asic Engineer Interview Questions
1,076 asic engineer interview questions shared by candidates
About the things in Resume
What is setup time/ hold time violation ? How are they related to the frequency.
Array, system verilog,uvm, mailbox Queue fifo configdb etc
Explaining the concepts of setup time and hold time in digital chip design
Wie funktionieren Flip Flops? Wie funktioniert SerDes?
Search a long string and return the index in where a substring appears in that string.
Design a state machine for an elevator with buttons 1, 2, 3, 4, up, down
Basic questions on timing. Live coding session about OOP
There were three technical round in that they ask whatever protocol you know or mention in your resume. They ask about STA, CDC, Process of Vivado RTL flow. They also ask logical riddle to check your logical thinking.
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