Recent salaries shared by ASIC Design Verification Engineer at MaxLinear
Job Title | Years of Experience
Total Pay
Base • Additional pay
Location
Date submitted
Job Title | Years of Experience
Location
Date submitted
Total Pay
Base • Additional pay
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MaxLinear pay FAQs
- The average salary for ASIC Design Verification Engineer is $141,609 per year (estimate) in US, which is 880% higher than the average MaxLinear salary of €14,451 per year (estimate) for this job.
- The salary trajectory of a ASIC Design Verification Engineer ranges between locations and employers. The salary starts at €0 per year (estimate) and goes up to €0 per year (estimate) for the highest level of seniority.
- The estimated average salary for a ASIC Design Verification Engineer at MaxLinear is €185,995 per year or €89 per hour, but some professionals have reported earning up to roughly €279,118 per year (90th percentile). The typical pay range is between €152,022 (25th percentile) and €231,034 (75th percentile) annually. This is based on 1 salaries submitted by MaxLinear ASIC Design Verification Engineer professionals on Glassdoor, as of Jun 2026.
