There's a circuit diagram of a pulse generator: a 2-input NAND gate with one of the inputs three inverters downstream from the other input, with some propagation delay for each inverter. Given the timing diagram of the input, what does the output look like?
A question of logic - very simple
AXI protocol and SV and UVM
Project overview, tech stack, Ai/ml
uvm tb structure, missing code completion, pointing to errors. factory overwrites etc.
Did you encounter any conflict with your colleague or team member?
Nothing out of the ordinary.
C++ - classes and virtual functions, abstract.
How do you find if the memory is little or big endian
a brief description of yourself and resume
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