Assertions,SV OOPS, Comp Arch
Verification Interview Questions
3,649 verification interview questions shared by candidates
UVM and verification questions mainly
During the interview, I was asked questions related to my experiences in the field. Setup hold, clock multiple. Specifically, discussions centered around the technical aspects of clock multiple, as well as an exploration of my work experiences and the responsibilities associated with my role.
Explain Timing Diagram in VLSI
1) Tell me about yourself 2) Tell me about the projects on your resume
-General digital flow design -General UVM verification questions
How do you verify this logic block?(a black box with some input and outputs and the timing diagram is given
General discussion on my coding background and course work
Why is MOESI better than MESI
The first team I interviewed with asked about: Computer architecture basics: Pipelines, branching and hazards, and hardware-based computer organization themed questions. The questions were along the lines of: 1) Tell me about the performance implications of a deep pipeline. 2) What do "volatile" and "virtual" mean in programming? 3) Define RISC vs. CISC differences. They also asked questions on course work in progress, completed, and projects listed on my resume. The second interview team was more behavioral, asking questions about projects and coding experiences.
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