write a complete AXI packet class in UVM
Verification Interview Questions
3,655 verification interview questions shared by candidates
basic resume, metastability, race condition, how classes are destroyed in SV?, basic object oriented concepts.
- timing questions: setup, hold, slack, critical path, max frequency, what is STA, how to improve the timing, etc
Q: Number of test vectors for a priority encoder with "n" inputs.
Q: FSM for detecting a particular sequence.
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Deep copy vs shallow copy in systemVerilog
What is coherency, consistency, difference. How do you ensure them, protocols, practices. How do you verify them (project related stuff). Questions on UVM, SystemVerilog and Verilog
SV UVM knowledge DV knowledge Qs on RTL GLS IP specific questions background and asking to debug a piece of code
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