UVM Phases, why do we use Virtual, Constraints , Use of randc , assertions , how do you override , how do you analyze verification metrics, callbacks
Verification Interview Questions
3,655 verification interview questions shared by candidates
Blocking vs non blocking in Verilog and Logic Design. Pipelining concept. Basic algorithms, time/space complexity. Virtual functions in C++
Online interview: 1. What is polymorphism ? 2. Design a 3 bit shift register in verilog RTL ? 3. For a FIFO design, what kind of assertions will you write(what conditions would you check for proper functioning of the FIFO) ?
What is an isolation cell?
Setup/hold time problem; meta-stability; 5-stage pipeline
data types in system verilog, test cases for memory designs, flipflop design
How do you find common elements between the arrays? reduce the complexity, asked me to write the code
First interview: describe a FSM for the result of a sequence of binary input mod 5. Merge sort. Second : C/ verilog coding.
Sorting, bit logic
What is crosstalk? Ways to fix crosstalk? Relationship between Resistance/Capacitance to Length & Width What is charge sharing? How to fix? What is body effect? What is short channel effect? List several effects.
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