Set up and Hold time, Latch and FIFO, FSM, String and Pointer in C,
Verification Engineer Interview Questions
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The memory size of STL bit set
Easy interview.
Verification of the DUT
OOPS, SV, UVM and Cache
setup and hold time, flip-flop/latch design, how would you verify a design?
i have mentioned all the interview question above
basic question about UVM and some verilog coding
describe a situation where I applied low-power design techniques to improve chip performance.
1. ATPG design basics 2. BISTs modes of work vs defects. 3. CDC testing
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