Assertions,SV OOPS, Comp Arch
Verification Engineer Interview Questions
2,558 verification engineer interview questions shared by candidates
UVM and verification questions mainly
During the interview, I was asked questions related to my experiences in the field. Setup hold, clock multiple. Specifically, discussions centered around the technical aspects of clock multiple, as well as an exploration of my work experiences and the responsibilities associated with my role.
Explain Timing Diagram in VLSI
1) Tell me about yourself 2) Tell me about the projects on your resume
-General digital flow design -General UVM verification questions
Question on Project, tool awareness, uvm methodology, driver code and testplan development.
What is the challenge you face when you start a New job?
They asked detailed questions about memory and interconnect design in advanced systems. They also gave me a small assignment which I had to do online.
Verification of a processor core - caches/interrupt etc
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