What classes did you like/dislike?
Verification Engineer Interview Questions
2,566 verification engineer interview questions shared by candidates
Do you know object-oriented code?
About Verification Techniques
System Design questions, particularly those related to testing systems
what do u know about virtual pages
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
C++, SystemVerilog basics
if I talk to your previous boss, what he/she/they gonna say about you?
Some question related to accessing analysis ports in a sequence ( via sequencer)
Difference between verilog and sv.? Basic interface questions.
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