question on packet transfer inside of test bench from generator to driver... (system verilog concepts)
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Perl questions, Propose test plan for round robin arbiter
Given an async fifo, tell the testplan --> complicated fifo with lot of requirements..(writes are done by 3 masters. there is an arbiter).
what is blocking and non blocking?
Write a logic to find a maximum number among the three given numbers.
There were 4 rounds - 3 technical and 1 HR.
Systemverilog assertions and constraints questions
They asked to code using Verilog.
4. explain interrupt handling, and various scenarios
7. hr questions
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