write a program
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
The cost of a stock on each day is given in an array. Find the maximum profit that you can make by buying and selling on those days. If the given array of prices is sorted in decreasing order, then profit cannot be earned at all.
Design a state machine to detect bit sequence. How do you verify it?
Q: How to calculate the depth of FIFO?
NA
How to make nor gate using two input mux
Describe what tests need to be done on memory
Explain how setup time and hold time violations occur and what can be done to reduce there occurence? What is metastability?
Difference between latch and flip flop, Sequence detector design, Divide by n circuits for different values of n. Few scenarios of assertions, Verilog code for positive edge detector and negative edge detector, Setup and Hold time and few codes to debug and provide output. basic questions in digital on mux, questions on code synthesizing
UVM, SystemVerilog and PCIe protocol
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