define tlm fifo's?
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Digital and SV ,UVM verilog basis
Basic sv and uvm and some digital verilog.
FIFO, LIFO in Verilog
Lcm, Swap, Factorial for C coding Write constraints in system verilog
Where do you see yourself in 5 years?
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.
1. Overall was on project 2. UVM methodologies and SV 3. Have been asked on logical reasoning 4. Queries on verilog, RTL coding were asked. 5. OOPS based concepts ,Polymorphism, Inheritance, Arrays methods, stacks ,Queues, Multidimensional arrays ,Vectors
How to have accurate testing when you a large test case to cover.
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