FiFo depth, Assertions, FSM, Clocks
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
1. FSM to check if a number is divided by 5. 2. Implement basic logic gates using a MUX and NAND. 3. Reverse a linked list. 4. Questions about a FIFO
pipeline processor architecture, hazard, shared memory problem, cache issues—remote repeated words both in SystemVerilog. I answered how to do it in python, but he insisted Con using c or SystemVerilog. In the last question, he asked me why I choose design verification. The whole procedure lasts about 53 minutes, quite tense I would say. I did not answer the memory coherence and delete repeat words in C. I would say I did not do it well. Hoping this could help others to get job. Just preparing questions.
Memory allocation
Create a presentation on your past projects.
Build a finite state machine with binary series input that accepts only numbers divided by 5
How do you access a register and confirm it is 12 bit or not?
What captivated your interest in joining Baxter?
Describe Yourself, project related question.
Testing methodologies and Test case scenarios
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