what is a good requirement?
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
Pipelining, FSM pattern generator, Digital logic (simple)
TDM (time division multiplexing) working and its corner cases .. FIFO questions
FSM, timing issue, perl
Virtual memory management
It was a group dealing with timing, so basically some tools related to timing analysis.
what is the use of explicit keyword in c++? what ate smart pointers
quetions regarding RC circuits and opamps
Full adder code, Gave some verilog codes to debug and find errors, Digital questions and Aptitude is important
UVM, SV concepts
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