polymorphism
Verification Engineer Interview Questions
2,565 verification engineer interview questions shared by candidates
The interview with HR is simple, but interview with the director is technical! Questions depend on the exam.
It was Basic verification questions
Natural numbers Prime number Cube question cheppaga adhi Oka de question Randomisation use chesi oka game cheyyali Random ga generate Aina values ni nuvvu guess cheyyali test bench lo Avi match aithe pass Lekapothe fail 0,1,0,0,2,0,0,0,3.....
Uvm factory mechanism System verilog basics
In a cubical room, there is a lizard in one corner, and he wants to go to the corner in the opposite end of the room. Dimensions of the room are given. What is the least distance it'll have to cover?
The question about cache coherency.
there is nothign most difficult . if u dont know jst say "i dont know".
SV and UVM basics Logical questions
They asked about more on verilog coding, system verilog data types, uvm phases. Constraints, assertions and mathematical questions
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