DV related, protocols, sv, uvm, axi,abp
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
Cache Coherency, UVM and TLM related, SV concepts, Past projects.
They asked about uvm fundamentals. They were looking for strong uvm experience and asked me to write code for scoreboard, monitor and asked about how to connect them.
design an electrical circuit with switches, voltage source for a particular application- wasn't expecting one since my area of expertise is mostly digital
2 signals, both only toggle once. At the first rising edge, start testbench; At the second falling edge, stop testbench. How?
Memory Consistency
Design an FSM for a 2-clock system
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
What is gray code and 8b10b encoding, and why they are useful
Q. What are all run-phases and in detail discussion about it Q. Basic constraints related to dist, and assertion
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