Memory allocation
Verification Design Engineer Interview Questions
953 verification design engineer interview questions shared by candidates
1. FSM to check if a number is divided by 5. 2. Implement basic logic gates using a MUX and NAND. 3. Reverse a linked list. 4. Questions about a FIFO
Questions mostly about the project. Basics of Pcie protocol
Explain the structure of uvm verification environment.
Describe Yourself, project related question.
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
Where do you see yourself in 5 years?
It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.
How to have accurate testing when you a large test case to cover.
FIFO, LIFO in Verilog
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