1. They asked me to explain a flip flop function with wave forms and an rtl programme in Verilog. 2. I was given a sequence of input waveform and was asked to design a state diagram and also to write an rtl code in Verilog 3. Functionalities of the Universal gates, clocking domains, STA, few analogue questions 4. To explain the previously done projects of my academic qualification in detail
For a six-deep FIFO with one (and two clocks), push and pop operations, what specific test cases will you use to verify the design?
Questions on projects that I did
Concentrate on your assertion concepts
Difference Between Associative array and Dynamic Arrya
How would you solve the Josephus problem.
Universal verification metrology U.V.M ??
how to use UVM events and UVM pool
Setup time and hold time
Microcontroller and processor, and digital circuits
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