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(manager basic fundamental knowledge questions) - What is the FPGA design flow? - What strategies do you use to get timing closure? - Write RTL code (Verilog or VHDL) that reserves bit order of a vector (i.e., 8 bit ).
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Staff Design Engineer

Interviewed at Microchip Technology

3.6★
Jun 15, 2020

(manager basic fundamental knowledge questions) - What is the FPGA design flow? - What strategies do you use to get timing closure? - Write RTL code (Verilog or VHDL) that reserves bit order of a vector (i.e., 8 bit ).

3 leetcode style interviews each with 2 questions, the first question is probably an easier medium difficulty and the second a solid to harder medium difficulty. All questions asked were included in the LeetCode meta question section.
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Staff IOS Engineer

Interviewed at Meta

3.6★
Nov 30, 2024

3 leetcode style interviews each with 2 questions, the first question is probably an easier medium difficulty and the second a solid to harder medium difficulty. All questions asked were included in the LeetCode meta question section.

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