UVM methodology related question about 1. Virtual interface 2. Fork join 3. UVM create and resource_db() usage. Some questions on Code coverage closure. I was asked to write c/sv code for cdc fifo and build a verification environment around it and simulate fifo full and fifo empty conditions
Senior Design Engineer Interview Questions
1,072 senior design engineer interview questions shared by candidates
Skillset: CPU Architecture, ISA knowledge, Digital Design, FSM design
What are the different pipelining stages and related
Describe the I2C interface Verilog code and the use of tristate buffers while making an I2C master module. Describe what is CAS latency
Who are you and what you did?
Question can vary from domain to domain
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What are the different ways of implementing metrology front-ends in meters? What are the pros and cons of each option?
What’s your typical workflow for modeling?
Write from your memory detail equations from your college days...
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