Draw Full and half adder circuits. Draw a 4-bit adder circuit. Draw 2 state counter. Draw NAND gate using CMOS. What is logical effort? What are LVT cells and how does leakage is affected using them? Solving some Gate-based and Boolean algebra-based questions.
Eco implementation in signoff stage
Setup-Hold timing inter-relationship question, framed by way of max frequency of operation
Provided a waveform and asked to design a circuit for that.
In the interview they asked about the projects
Technical and motivation
STA questions related to generated clocks
questions based on MOSFETs, power gating,clock gating and my projects.
Power gating, clock gating etc
explain synthesis process, and problem.
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