Clock tree synthesis, STA
Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
Tell me about yourself
Upf commands CTS and power relation Mscts advantages Low power techniques
they asked about my project, what all physical cells that I know, what is ICG and some aptitude questions
what is vlsi? fabrication process of cmos external biasing of cmos Transfer characteristics of CMOS Cmos logic gate with truth table what are sequential Flip flops truth table of flip flops timing diagram of d flip flop some basics about semiconductor and biasing process
Explain setup and hold timing
Extensive discussion based on every flow topics, project experience.
D FF transmission gate implementation, then gave delays of the jam latch and the TG, asked to tell the setup and hold time.
What are the steps in physical design flow..? Explain about all the steps.?
Explain the operation of MOSFET with current equations.?
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