What is setup and hold time
Physical Design Engineer Interview Questions
595 physical design engineer interview questions shared by candidates
when Capacitors in series or parallel what happens to charge and voltage
XOR with 2:1 MUX Edge detection Circuit Setup and hold time their violations Why do we need them what can you do to reduce them what would you do to correct s&h time after fabrication
They asked about the projects on the resume and basic questions about timing
most complicated block i have ever done in apple
you have 2 types of balls, red and white, you have 3 boxes 1 with red balls, 1 with white balls, 1 combined. the boxes are labeled with stickers. the stickers are not correct! one box marked as "red" second box is marked as "white" third box is marked as "combined". how many tries you need to know which box is realy the red,white and combine.
Describe what you did. (based on your resume)
the interviewer gave me scheme of two blocks, in the left block (block A) there were 2 FF, FFa and FFb. in block B there were only logic. FFa routed through logic to block B, and returned through logic to FFb in Block A. the interviewer tell me that is 150ns delay in the timing path between FFa and FFb, and ask me to describe what can be the cause and how to fix it.
What's constraints you gave to your design?
How to resolve Placement congestion.
Viewing 141 - 150 interview questions