Why does the PCIe spec limit the time skew of a common clock architecture to less than 12 ns skew between the clock routed to the transmitter side and the sum of the clock routed to the receiver side PLUS the routing length of the TX lane to the receiver.
To tell them about my most recent projects
Can you describe a challenging signal integrity problem you encountered in a previous project and how you resolved it?
.Transmission line theory
A differential pair is routed as a microstrip and the weave of the FR4 causes the er on one of the signals in the pair to vary a lot from the other member of the pair (think egregious, 3.4 on one, 4.5 on the other). What effects can you expect and what can you do to mitigate.
What makes you a good candidate for this job?
Technical questions related to the assets of the Central Facility Processing such as Piping, tanks, and vessels. other questions related to the Inspections and test Plan related to API and RBI. other deep questions are related to Non-Destructive Testing NDT.
Details on a PLL - loop bandwidth filter selection choice and detailed technical explanation.
Lots of questions about stackups, and how you would advise designers early in the design process to avoid SI and PI issues
What is the most important figure of merit with signal integrity?
Viewing 1 - 10 interview questions