Traffic light design in verilog code, Pipelining, one round on system veilog and coding, one round on analyzing Architecture and data related to it, Sequence detector, optimizing the given verilog code, circuit diagram from the code(what will it synthesize to), array questions in Perl.
The questions are as follows : Difference between validation and verification ? What is Race condition? Difference between Latch and flipflop? How to design ROM? What is a State machine? Cycle driven and event driven simulation differences and which one is better Functional and code coverage differences Blocking and non-blocking assignments in Verilog How to define variables in Verilog? $display and $monitor differences Setup and hold time Hold time violation Mesi protocol Page table DRAM and SRAM differences and how to design them
Asked about basic digital logic questions and questions related to coding verilog/vhdl. question on the resume and the position.
STA concepts and problems, Implementation of all logic gates using muxes, clock gating circuits, inputs and outputs at every stage of ASIC and Physical Design flows
It was around 30 minutes discussion only on D flip-flops. No other topic was asked.
traverse binary tree
linked list run time and binary trees
capacitor charging and discharging
Describe some logic gates
What happens to the speed of a transistor when the threshold voltage is raised?
Viewing 3221 - 3230 interview questions