Design a FIFO hardware
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Spoke about some post silicon validation. Haven't had much experience working in the lab so it didn't matter.
In interview 1, they asked basics of digital elex , c programming , memory architecture in c. In interview 2 they asked to code traffic light controller in verilog.
given a mem module of 1KB which can accept 1 read or 1 write at once, how can you create from 5 modules a big memory which can support 2 reads or 1 write at once of 4K?
what is OCV?
Write verilog module and test bench for 8bit counter and 4:1 MUX
Design a 2-bit shift register.
In Verilog, what's the difference between "if ... else ..." and "case"?
There were 2 rounds of interview. each had 3 panels. every interviewer asked about the project. then there were basic questions from Digital Electronics, C programming.
Practical problems(fifo, counter etc) and asked to setup the verification flow around them.
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