Previous projects and experiences regarding FPGA
Fpga Engineer Interview Questions
542 fpga engineer interview questions shared by candidates
What are the clock crossing techniques?
How do you cross data between two clock domains of 40 MHz and 70 MHz?
Given you've generated an 80MHz, and 50MHz clock, how do you manage data crossing between these two clock domains?
Logic Design Questions
A RTL coding question on how to model a signal going from one clock domain to a slower clock domain.
how ping pong buffer will works?
HR interview: - Generic HR questions. Engineer interview: - VHDL vs verilog - Latches in FPGAs - Multipath constraints - Synchronisers
General FPGA and RTL questions. Some seemed kind of outdated as well.
Can you share with me the confidential information without leaking confidential information
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